Некоторые используемые чипы

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vasek00
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PostPosted: Wed Jul 30, 2014 13:27    Post subject: Некоторые используемые чипы Reply with quote
Atheros AR9331частота 400MHz
Code:
The Atheros AR9331 is a highly integrated and cost effective IEEE 802.11n 1x1 2.4 GHz Systemon-a-Chip (SoC) for wireless local area network (WLAN) AP and router platforms. In a single chip, the AR9331 includes a MIPS 24K processor, five-port IEEE 802.3 Fast Ethernet Switch with MAC/PHY, one USB 2.0 MAC/PHY, and external memory interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio interface, SLIC VOIP/PCMinterface, UART, and GPIOs that can be used for LED controls or other general purpose interface configurations.
The AR9331 integrates two Gbit MACs plus a five-port Fast Ethernet switch with a four-traffic class Quality of Service (QoS) engine.
The AR9331 integrates an 802.11n 1x1 MAC/BB/ radio with internal PA and LNA. It supports 802.11n operations up to 72 Mbps for 20 MHz and 150 Mbps for 40 MHz channel respectively,
and IEEE 802.11b/g data rates. Additional features include on-chip one-time programmable (OTP) memory.

Features:
- Complete IEEE 802.11n 1x1 AP or router in a single chip
- MIPS 24K processor operating at up to 400 MHz
- External 16-bit DDR1, DDR2, or SDRAM memory interface
- SPI NOR Flash memory support
- No external EEPROM needed
- 4 LAN ports and 1 WAN port IEEE 802.3 Fast Ethernet switch with auto-crossover, auto polarity, and auto-negotiation in PHYs
- Four classes of QoS per port
- Fully integrated RF front-end including PA and LNA
- Optional external LNA/PA
- Switched antenna diversity
- High-speed UART for console support
- I2S/SPDIF-out audio interface
- SLIC for VOIP/PCM
- USB 2.0 host/device mode support
- GPIO/LED support
- JTAG-based processor debugging supported
- 25 MHz or 40 MHz reference clock input
- Advanced power management with dynamic clock switching for ultra-low power modes


Atheros AR9344 частота 533MHz
Code:
The Atheros AR9344 is a highly integrated and feature-rich IEEE 802.11n 2x2 2.4/5 GHz Systemon-a-Chip (SoC) for advanced WLAN platforms.
It includes a MIPS 74Kc processor, PCI Express 1.1 Root Complex and Endpoint interfaces, five port IEEE 802.3 Fast Ethernet Switch with MAC/PHY, one MII/RMII/RGMII interface, one USB 2.0 MAC/PHY, and external memory interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio interface, SLIC VOIP/PCM interface, two UARTs, and GPIOs that can be used for LED controls or other general purpose interface configurations.
The AR9344 supports 802.11n operations up to 144 Mbps for 20 MHz and 300 Mbps for 40 MHz respectively, and 802.11a/b/g data rates.
Additional features include Maximal Likelihood (ML) decoding, Low-Density Parity Check (LDPC), Maximal Ratio Combining (MRC), Tx Beamforming (TxBF), and On-Chip One-Time Programmable (OTP) memory.
The AR9344 PCIE Root Complex interface can be used to connect to another Atheros single-chip MAC/BB/radio for dual concurrent WLAN applications. The AR9344 supports booting from either NOR or NAND flash.If NOR flash is used
as boot codestore, an additional NAND flash device can still be connected, for end-user multimedia storage and other applications.
When connecting the AR9344 to an external host through the PCIE Endpoint interface, or the USB Device interface, the AR9344 can off load the host CPU from computation- intensive functions, allowing it to focus on its dedicated tasks.

Features:
- 74Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, operating at up to 533 MHz
- External 16- or 32-bit DDR1, DDR2 operating at up to 200 MHz (400 M transfers/sec), or 16-bit SDRAM memory interface operating at up to 200 MHz
- NAND and SPI NOR Flash memory support
- 10/100 Ethernet Switch with five IEEE 802.3 Ethernet LAN ports
- MII/RMII/RGMII interface
- 802.3az Energy Efficient Ethernet compliant
- Hardware-based NAT & ACL accelerators for Ethernet interface
- Both PCI Express 1.1 Root Complex and Endpoint interfaces supported simultaneously
- One USB 2.0 controller with built-in MAC/PHY supports Host or Device mode
- Boot from external CPU via PCIE, USB, xMII, eliminating need for external flash
- I2S/SPDIF-out audio interface
- SLIC for VOIP/PCM
- One low-speed UART (115 Kbps), one highspeed UART (3 Mbps), and multiple GPIO pins for general purpose I/O
- Fully integrated RF Front-End including PAs and LNAs
- Optional external LNA/PA
- 25 MHz or 40 MHz reference clock input
- 1.2 V switching regulator
- Advanced power management with dynamic clock switching for ultra-low power modes


Atheros AR7242 частота 400MHz
Code:
The Atheros AR7242 is a high performance and cost effective network processor for access point, router, and gateway applications. It includes a MIPS 24Kc processor, PCI Express 1.1 host interface, integrated 10/100Mbps Fast Ethernet MAC/PHY, one RGMII port, one USB 2.0 MAC/PHY, and external memory interface for serial Flash, DDR1 or DDR2 interface, an I2S audio interface, a high-speed UART, and GPIOs that can be used for LED controls or other general purpose interface configurations.
The AR7242 is a memory-centric architecture including various DMA controlled interfaces that access the DDR memory.
The AR7242 network processor, when paired with the AR928x/AR938x/AR939x single chip 802.11n MAC/BB/Radio family, provides the best-in-class WLAN solution capable of supporting 802.11b/g/n standards.

Features:
- Integrated MIPS 24 K 32-bit processor operating at up to 400 MHz
- 64 K instruction cache and 32 K data cache
- Integrated 10/100 802.3 Ethernet LAN port and one RGMII port
- 16-bit DDR1 or DDR2 memory interface supporting up to 400 M transfers per second
- An external serial Flash memory interface (maximum 16 MBytes)
- One USB 2.0 controller with built-in MAC/PHY
- High-speed UART and multiple GPIO pins for general purpose I/O or LED control
- A single lane PCI Express 1.1 interface that can be used for interfacing to the AR928x/AR938x/AR939x single chip 802.11n MAC/BB/Radio
- JTAG port support for processor core


Atheros AR9280 Single-Chip 2x2 MIMO MAC/BB/Radio with PCI Express Interface for 802.11n 2.4 and 5GHz WLANs
Code:
The Atheros AR9280 is a highly integrated single-chip solution for 2.4 and 5 GHz 802.11n-ready wireless local area networks (WLANs) that enables high-performance 2x2 MIMO configurations for wireless station applications demanding robust link quality and maximum throughput and range. The AR9280 integrates a multi-protocol MAC, baseband processor, analog-to-digital and digital-to-analog (ADC/DAC) converters, 2x2 MIMO radio transceiver, and PCI Express interface in an all-CMOS device for low power and small form factor applications.
The AR9280 implements half-duplex OFDM, CCK, and DSSS baseband processing, supporting up to 130 Mbps for 20 MHz and 300 Mbps for 40 MHz channel operations respectively, and IEEE 802.11a/b/g data rates. Additional features include signal detection, automatic gain control, frequency offset estimation, symbol timing, and channel estimation. The AR9280 MAC supports the 802.11 wireless MAC protocol, 802.11i security, receive and transmit filtering, error recovery, and quality of service (QoS).
The AR9280 supports two simultaneous traffic streams using up to two integrated transmit chains and receive chains for high throughput and range performance. Transmit chains combine
baseband in-phase (I) and quadrature (Q) signals, convert them to the desired frequency, and drive the RF signal to multiple antennas. The receiver converts an RF signal to baseband I and Q outputs. The frequency synthesizer supports one-MHz steps to match frequencies defined by IEEE 802.11a/b/g/n specifications.
The AR9280 supports frame data transfer to and from the host using a PCI Express interface that provides interrupt generation and reporting, power save, and status reporting. Other external interfaces include serial EEPROM and GPIOs.
The AR9280 is interoperable with standard legacy 802.11a/b/g devices.

Features:
- Dynamic frequency selection (DFS) in required 5-GHz bands
- All-CMOS MIMO solution interoperable with IEEE 802.11a/b/g/n WLANs
- 2x2 MIMO technology improves effective throughput and range over existing 802.11a/b/g products
- Supports spatial multiplexing, cyclic-delay diversity (CDD), and maximal ratio combining (MRC)
- 2.4/5 GHz WLAN MAC/BB processing
- BPSK, QPSK, 16 QAM, 64 QAM, DBPSK, DQPSK, and CCK modulation schemes
- Data rates of up to 130 Mbps for 20 MHz channels and 300 Mbps for 40 MHz channels
- Wireless multimedia enhancements quality of service support (QoS)
- 802.11e-compatible bursting
- Support for IEEE 802.11e, h, and i standards
- WEP, TKIP, and AES hardware encryption
- PCI Express 1.1 compatible
- 20 and 40 MHz channelization
- Reduced (short) guard interval
- Frame aggregation
- Block ACK
- Support for 2- or 3- wire Bluetooth coexistence
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vasek00
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Joined: 06 Nov 2010
Posts: 3295

PostPosted: Wed Jul 30, 2014 13:36    Post subject: Re: Некоторые используемые чипы Reply with quote
Atheros AR7240 частота 400MHz
Code:
The Atheros AR7242 is a high performance and cost effective network processor for access point, router, and gateway applications. It includes a MIPS 24Kc processor, PCI Express host interface, integrated 802.3 Ethernet wich five 10/100 Mbps Fast Ethernet MAC/PHY, one USB 1.1 MAC/PHY, and external memory interface for serial Flash, DDR1 interface, a high-speed UART, and GPIOs that can be used for LED controls or other general purpose interface configurations.
The AR7240 is a memory-centric architecture including various DMA controlled interfaces that access the DDR memory.
The AR7240 network processor, when paired with the AR928x single chip 802.11n MAC/BB/Radio family, provides the best-in-class WLAN solution capable of supporting 802.11b/g/n standards.

Features:
- Integrated MIPS 24 K 32-bit processor operating at up to 400 MHz
- 64 K instruction cache and 32 K data cache
- Integrated Ethernet switch with four 10/100 802.3 Ethernet LAN port and one WAN port
- 16-bit DDR1 memory interface supporting up to 400 M transfers per second
- An external serial Flash memory interface (maximum 16 MBytes)
- One USB 1.1 controller with built-in MAC/PHY
- High-speed UART and multiple GPIO pins for general purpose I/O or LED control
- A single lane PCI Express 1.1 interface that can be used for interfacing to the AR928x single chip 802.11n MAC/BB/Radio
- JTAG port support for processor core


AR8327/AR8327N Seven-port Gigabit Ethernet Switch
Code:
The AR8327 is a highly integrated seven-port Gigabit Ethernet switchwith non-blocking switch fabric, a high-performance lookup unit with 2048 MAC address, and a four-traffic class Quality of Service (QoS) engine. The AR8327 has the flexibility to support various networking applications. The AR8327 is designed for costsensitive switch applications in wireless AP routers, home gateways, and xDSL/cable modem platforms.
The AR8327 integrates all the functions of a high-speed Switch system, including packet buffer, PHY transceivers, media access controllers, address management, and a nonblocking switch fabric into a single 0.11 um CMOS device. It complies with 10BASE-Te, 100BASE-Tx & 1000BASE-T specifications, including the MAC control, pause frame, and auto-negotiation subsections, providing compatibility with all industry-standard Ethernet, Fast Ethernet & Gigabit Ethernet networks.
The AR8327 device contains five full-duplex 10BASE-Te/100BASE-TX/1000BASE-T transceivers and 10BASE-Te/100BASE-TX can run at half duplex, each of which performs all of the physical layer interface functions for 10BASE-Te Ethernet on Category 5 unshielded twisted-pair (UTP) cable and 100BASE-TX Fast/Gigabit Ethernet on Category 5 UTP cable. The remaining 2 ports feature a standard GMII/RGMII/MII/Serdes interface to allow connection to a host CPU in PON/xDSL/Cable/Wifi/Fiber routers. The media access controllers on the AR8327 also support Jumbo Frames which are typically used for highperformance connections to servers because they offer a smaller percentage of overhead on the link for more efficiency. MDC/MDIO or EEPROM interfaces provide easy programming of the on-chip 802.1p QoS and/or DiffServ/TOS. This allows switch traffic to be given different classes of priority or service - for example, voice traffic for IP phone applications, video traffic for multimedia applications, or data traffic for e-mail. Up to 4K Virtual LANs (VLANs) can be set up via the MDC/MDIO port for separation of different users or groups on the network. ACL features can reduce CPU effort for VLAN/Q.O.S/DSCP/Forward mapping & remapping based on layer1 to Layer4 information. 16 PPPoE header add/removal can increase Video quality and offload the CPU. Hardware IGMP V1/V2/V3 is an innovation for IPTV service.
Green Power can increase energy efficiency for no link or idle states.
The AR8327N chip supports hardware NAT (Network Address Translation) to offload the CPU and achieve the full wire speed when doing NAT.
The AR8327/AR8327N supports the following modes of NAT.
1. Basic NAT: This involves IP address translation only, not port mapping.
2. Network Address Port Translation (NAPT):
This involves the translation of both IP addresses and port numbers. For the NAPT mode, the AR8327/AR8327N can support
Full cone NAT, Restricted cone NAT, PortRestricted cone NAT and Symmetric NAT.
AR8327/AR8327N supports the following configurations
- 5*10/100/1000Base-T + GMII/RGMII/MII + 1* Serdes
- 5* 10/100/1000Base-T + 2*RGMII/MII
- 4* 10/100/1000Base-T + 1*RGMII/MII + 1* Single RGMII PHY

Features:
The AR8327 chip family includes a 7-port MAC structure to support the following family of switch chips:
- Supports 802.3az Power Management
- The AR8327N chip includes the Hardware NAT (Network Address Translation) function
- The AR8327 chip (without the ‘N’ designation) does not contain the Hardware NAT function
- ACL Mask Rule from Layer1~4. Port No, DA, SA, Ethernet Type, VLAN, IP Protocol, IPv4/v6 Source/Destination Address, TCP/UDP Source/Destination port
- 96 ACL Mask Rule for Pass/Drop, VLAN/Q.O.S./DSCP Mapping/Translation
- User define ACL up to 48 bytes depth in Layer 4/3/2
- Q.O.S mechanisms include Weight Round Robin, Strict, Hybrid Up Queue
- Port Base VLAN & 4K 802.1Q VLAN Group
- IVL & SVL
- IGMP Snooping V1, V2 & V3. IPv6 MLD V1/V2 forwarded to CPU
- Supports Light Hardware IGMP snooping v1/v2/v3, MLDv1/v2 and Smart Leave
- Hardware Looping Detectionn QinQ function for SVLAN & CVLAN Translat ion
- IP Packet/PPPoE bypass to reduce CPU loading on Video packet
- 16 PPPoE session support/PPP Session Header Removal/Addition
- Scalable Ingress/Egress Bandwidth Control
- 40 MIBs Counter/Port & Port Status.
- 1M Bit Packet Buffer
- Supports 9K Jumbo Frame
- Port Mirror, 802.1X Security, Rapid Spanning Tree
- Rule-based Bandwidth Control
- Programmable Wake on LAN
- Half Power Mode for Cable length less than 30m (for home installations)
- Supports Internal/External Loopback
- Supports Reduced AFE circuit
- 2K MAC Table. Edit, Search, Add & Delete.
- MAC Limit by Port/Chip/VLAN
- Trunking Function
- Supports Trunking and auto-failover
- Power Saving on Cable no Link, short Cable & 10BASE-Te Idle
- Supports 1K NAPT entries and 128 hardware based host routing (ARP) entries
- Supports hardware-based IP source guard, ARP inspection, routing/L3 switching
- Supports VLAN translation and mapping with 64 Translation entries
vasek00
DD-WRT Guru


Joined: 06 Nov 2010
Posts: 3295

PostPosted: Wed Jun 24, 2015 16:14    Post subject: Re: Некоторые используемые чипы Reply with quote
Блок схема некоторых
vasek00
DD-WRT Guru


Joined: 06 Nov 2010
Posts: 3295

PostPosted: Wed Jun 24, 2015 16:25    Post subject: Re: Некоторые используемые чипы Reply with quote
AR7240
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